\begin{abstract}
In modern RF energy harvesting sensor nodes, nonvolatile SRAM (nvSRAM) has been widely investigated as a promising on-chip memory architecture due to its zero standby power, resilience to power failures and fast read/write operations. However, conventional backup schemes which transfer overall data from SRAM into NVM demand large on-chip switched capacitors and generate instantaneous high peak inrush current, which has a negative impact on energy efficiency and circuit reliability.

To mitigate these problems, we propose a novel systematic backup flow consisting of a partial backup process and a run-time pre-writeback scheme for nvSRAM based caches. A statistics based dead-block predictor is employed to achieve a fast and low power partial backup process. We also present a adaptive pre-writeback point allocation strategy to further reduce the backup load. Simulation results show that with our proposed recovery architecture, inrush current is reduced by \% on average and switched capacitance is reduced by \% on average compared with the conventional full backup scheme.

\end{abstract}
